1. Field of the Invention
The invention relates to a multiport memory useful for image processing.
2. Description of the Prior Art
A conventional semiconductor memory will be described with reference to FIG. 1. A row of a memory 1 of (M columns.times.N rows) elements is selected by the output of a decoder (DEC) 2 corresponding to the upper bits AU of an address. Connecting lines of the columns of the memory 1 are connected to a selector (SEL) 5, and under the control of the selector 5 responsive to lower bits AL of the address, read data DO is provided from the selector 5. The upper bits AU are log.sub.2 N bits, and the lower bits AL are log.sub.2 M bits. FIG. 1 shows only the read-out elements for simplicity.
Recently, dual port memory or a video memory suited for processing a video signal in the data sequence of raster scanning has been proposed. As shown in FIG. 2, this type of memory 1 has a port for serial output data SO. Clearly, only a row address AU is given to the decoder (DEC) 2, so that the data of one row is serially output by a shift register (SAM) 6, and the serial output into the shift register 6 in a parallel fashion, and output at an independent speed of the serial port.
The port for the output data DO of FIG. 1 is called a random access port, and the port for the output data SO of FIG. 2 is called a serial port. A memory in which both such ports are provided is called a dual port memory or video memory.
The dual port memory is useful in an image processing circuit. There is a case where plural serial ports are needed. Conventionally, in FIG. 2, it is possible to have two serial ports by providing another shift register 6' at a position indicated by a broken line therein. However, the provision of 3 or more serial ports is difficult.
3. Description of Related Art
For the provision of three serial ports as shown in FIG. 3, it is considered that shift registers SR1, SR2, and SR3 are connected in parallel to the column connecting lines of the memory 1 and serial outputs SO1, SO2, and SO3 are supplied from the respective shift registers. Shift clocks SCK1, SCK2, and SCK3 are supplied to the shift registers SR1, SR2, and SR3, and parallel load signals LD1, LD2, and LD3 are supplied from a control circuit (C) 4. In addition, upper bits AU1, AU2, and AU3 of addresses corresponding to the respective ports are supplied to the selector 3 selector (SEL) 3 for application to the decoder (DEC) 2, and one of these upper bits is selected by a control signal from the control circuit 4.
For instance, in response to the selection of the upper bits AU1 by the selector 3, the load signal LD1 is fed to the shift register SR1. As a result, row data accessed by the AU1 bit loaded in parallel to the shift register SR1. The data of the shift register SR1 is output as the serial data SO1 with the shift clock SCK1.
In the structure shown in FIG. 3, there is a need that the column connecting lines drive the three shift registers SR1, SR2, and SR3, and the load consequently becomes large as compared with that of only one shift register. A powerful driver (buffer circuit) has a large area as represented in FIG. 4A. In addition, as shown in FIG. 4B or FIG. 4C, it is possible to employ one middle-class driver and three drivers to enable the increase of drive capability. However, in any one of the structures shown in FIG. 4, the circuit size becomes large making it difficult to incorporate into the memory 1. As a result, the realization of a multiport memory having many serial ports is not achieved.